Low-loss coplanar waveguides

ABSTRACT

Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over a silicon substrate and a photoresist is applied and patterned to define areas where the signal line and the ground plane will be formed. A barrier layer is provided over the oxide layer in the defined areas. A metal layer is then deposited over the barrier layer. An etch mask is deposited over the metal layer for the subsequent trench formation. The photoresist and the underlying portion of the oxide and barrier layers are removed and a deep trench is formed in the substrate between the signal line and the ground plane using etching through the mask.

FIELD OF THE INVENTION

[0001] This invention relates to low-loss millimeter wave transmissionlines and, in particular, to coplanar waveguides or ground-signal-groundlines.

DISCUSSION OF THE RELATED ART

[0002] During the past three decades, a steady progress of silicon-basedintegrated circuit technology brought about the advent of ULSI devicesand sub-quarter micron features. Currently, such advanced technologiesare increasingly finding applications in both radio-frequency (RF)electronics and sensory electronics, and these technologies are expectedto combine the RF devices and sensors with ULSI on a chip for low costfabrication processes. Silicon micro-fabrication technologies have alsobeen applied to millimeter wave devices.

[0003] Current state-of-the-art millimeter wave devices for operating atfrequencies employing signals having a wavelength of one to tenmillimeters are traditionally constructed in a metal waveguide. Typicalconstruction techniques implement the traditional dimensional milling ofthe metal structure. However, since the waveguide dimensions areproportional to the operating wavelength, these dimensions becomesmaller as the frequency increases. As the frequency of the deviceincreases, exceeding 100 GHz, for example, the complexities oftraditional fabrication and the strict tolerances required becomeextremely difficult to achieve. In large quantity production schemes,traditional precision milling techniques are extremely costly inachieving the precision required for devices of all types ofapplications.

[0004] Millimeter wave devices are typically manufactured in coplanarwaveguide structures. A coplanar waveguide structure has one or moreclosely spaced, but separated, longitudinal coplanar signal conductorspositioned transversely between, and separated from, two adjacentlongitudinal coplanar ground conductors by respective gap widths.Frequency signals are carried along the facing edges of the signal toground conductors. The ground conductors may be much wider than the gapsbetween signal to signal or signal to ground.

[0005] Coplanar waveguides are particularly usefull because of thesimplified structure provided by having both signal and groundconductors on a single plane and the resulting access to the groundplanes on both sides of the signal conductor. Adjacent coplanarwaveguides are known to be used to connect different flip-mountedcircuits. The coplanar waveguides also provide improved isolationbetween signal conductors as compared to some other transmission linestructures.

[0006] Millimeter wave devices manufactured as coplanar waveguidestructures, however, are not practical because of the high dielectriclosses due to silicon substrates as well as high conductor losses due tointerconnections encountered at frequencies above 60 GHz.

SUMMARY OF THE INVENTION

[0007] The present invention provides coplanar waveguides which are morereliable and able to accommodate reduced circuitry dimensions andincreased frequencies, as well as methods of forming such coplanarwaveguides.

[0008] In an exemplary embodiment, a coplanar waveguide is providedhaving a deep trench between the signal line and the ground plane. Inone embodiment, an oxide layer is provided over a substrate and aphotoresist is applied and patterned to define areas for the signal lineand ground plane. A barrier layer is provided over the oxide layer inthe defined areas. A metal layer is deposited over the barrier layer. Anetch mask is deposited over the metal layer and the photoresist, and theunderlying portion of the oxide and barrier layers are removed to exposethe substrate surface. An outer silicide layer is also provided topassivate the exposed metal sidewalls and a deep trench is formed at theexposed surfaces of the substrate by anisotropic etching using the etchmask. In another embodiment, isotropic etching is used to form a deeptrench at the exposed surfaces of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above advantages and features of the invention will be moreclearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

[0010]FIG. 1 illustrates a cross-sectional view of a coplanar waveguidefragment constructed in accordance with a first embodiment of theinvention.

[0011]FIG. 2 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 1.

[0012]FIG. 3 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 2.

[0013]FIG. 4 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 3.

[0014]FIG. 5 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 4.

[0015]FIG. 6 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 5.

[0016]FIG. 7 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 1 at a processing step subsequent to thatshown in FIG. 6.

[0017]FIG. 8 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 6 at a processing step subsequent to thatshown in FIG. 6 and in accordance with a second embodiment of thepresent invention.

[0018]FIG. 9 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 7 at a processing step subsequent to thatshown in FIG. 7.

[0019]FIG. 10 illustrates a cross-sectional view of the coplanarwaveguide fragment of FIG. 7 at a processing step subsequent to thatshown in FIG. 9.

[0020]FIG. 11 is a schematic diagram of a processor system incorporatingthe coplanar waveguide constructed in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Exemplary embodiments of the present invention will be describedbelow in connection with the drawings. Other embodiments may be utilizedand structural or logical changes may be made without departing from thespirit or scope of the present invention. Although exemplary processconditions for forming various material layers are described below,these are only representative and are not meant to be considered aslimiting the invention.

[0022] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposedsemiconductor surface. Semiconductor-based structure must be understoodto include silicon, silicon-on insulator (SOI), silicon-on sapphire(SOS), doped and undoped semiconductors, epitaxial layers of siliconsupported by a base semiconductor structure foundation, and othersemiconductor structures. The semiconductor-based structures need not besilicon-based. The semiconductor could be silicon-germanium, germanium,or gallium arsenide. When reference is made to substrate in thefollowing description, previous process steps may have been utilized toform regions or junctions in the base semiconductor or foundation.

[0023] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 1-10 illustrate embodiments ofexemplary coplanar waveguides 100, 200 (FIGS. 9-10) fabricated inaccordance with methods of the present invention. FIG. 1 depicts aportion of a semiconductor substrate 12 on which an insulating oxidelayer 14 is formed by conventional methods of the prior art. In anexemplary embodiment of the invention, the semiconductor substrate 12 isformed of silicon (Si), and thus, reference to the semiconductorsubstrate 12 will be made in this application as to the siliconsubstrate 12. The silicon substrate 12 may have any crystallineorientation and, therefore, an advantage of the present invention isthat the formation of grooves and/or channels within the siliconsubstrate 12 which will form the coplanar waveguides of the presentinvention as it will be explained in more detail below, is notrestricted to a silicon substrate with <100> orientation, as in theprior art.

[0024] The oxide layer 14 (FIG. 1) may be formed by deposition, forexample, to a thickness of about 200 Angstroms to about 300 Angstroms.The oxide layer 14 reduces the dielectric loss in the silicon substrate12. Because silicon has a dielectric constant of about 12, which is highcompared to that of air, which is 1, most of the electric field linesand of the electric flux appear through the silicon, and not throughair. The electric field lines and the electric flux which concentrate inthe silicon substrate 12 further result in high losses in the substrate.The formation of the low dielectric constant oxide layer 14 above, andin contact with, the silicon substrate 12, and below signal conductorsas it will be described in detail below, minimizes the electric fieldand the electric flux in the conductive silicon substrate and minimizesthe losses.

[0025] Referring now to FIG. 2, a thick photoresist 16 of about 300,000Angstroms to about 500,000 Angstroms is patterned by photolithography,for example, to define openings 13 (FIG. 3) wherein signal conductorlines and ground conductor planes will be later formed, as will bedescribed below. After the exposure and development of the exposedportions of the photoresist 16, portions 16 a of the unexposed andundeveloped photoresist 16 and the openings 13 are formed over thesilicon substrate 12, as shown in FIG. 3.

[0026] A lift-off metallization process is next performed by depositinga barrier layer 18 in the openings 13 (FIG. 3) and over any exposedportions of the oxide layer 14, as shown in FIG. 4. The barrier layer 18may comprise bonding materials such as tantalum (Ta), titanium (Ti),titanium-tungsten (TiW), titanium nitride (TiN) or chromium (Cr), amongothers. The barrier layer 18 acts as a diffusion barrier layer and formsa strong mechanical and chemical bond between the conductive materialwhich will be formed later and the oxide layer 14 to help preventpeeling of the formed conductive material from the oxide layer. In apreferred embodiment of the invention, the barrier layer 18 is formed ofgraded titanium nitride (TiN). According to this embodiment, titanium isfirst deposited to a thickness of about 50 Angstroms to about 100Angstroms followed by titanium nitride deposition, by continuingevaporation of titanium in the presence of nitrogen, for example.

[0027] Next, as illustrated in FIG. 5, a conductive material 20preferably comprising copper (Cu) is formed to a thickness of about100,000 Angstroms to about 200,000 Angstroms to partially fill theopenings 13. According to an embodiment of the present invention, theconductive material 20 is deposited by thermal evaporation at or nearroom temperature, for example, but other suitable methods may beemployed also, as desired.

[0028] Copper (Cu) is preferred for the conductive material 20 becausecopper has a low electrical resistivity (1.67 micro-ohm/cm) which helpsto reduce conductor loss. Copper is also preferred because itsdeposition near or at room temperature minimizes the grain growth andprovides a smoother surface. Various studies have directly related thesurface roughness of a conductive material with conductor losses. Forexample, the correlation between surface roughness and improvements inthe RF losses has been studied by McGrath et. al. in SiliconMicromachined Waveguides for Millimeter-Wave and Submillimeter-WaveFrequencies, IEEE Microwave and Guided Wave Letters No. 3, p. 61 (March1993), the disclosure of which is incorporated by reference herein.According to this study, the conductivity of the gold plating of thecommercial waveguides typically employed in applications of the priorart is about {fraction (1/10)} that of copper, and McGrath et. al.concluded that the improvements in the gold surface are directly relatedto improvements in the RF losses. Thus, copper deposition at or nearroom temperature minimizes the grain growth and provides a smoothersurface, which in turn lower the losses.

[0029] Subsequent to the deposition of the conductive material 20, asilicon oxide layer 22, of silicon dioxide (SiO2) or silicon oxide(SiO), for example, is formed over the conductive material 20 tocompletely fill the openings 13, as also illustrated in FIG. 5. As itwill be described in more details below, the top silicon oxide layer 22is used as an etch mask during the trench formation and, thus, referenceto the silicon oxide layer 22 will be also made as to the mask layer 22.The silicon dioxide layer 22 may be deposited by thermal evaporation ator near room temperature, for example, to a thickness of about 5,000Angstroms to about 10,000 Angstroms, but other suitable methods may beemployed also, as desired. Further, any excess titanium nitride,conductive material and/or silicon oxide can be removed by chemicalmechanical polishing or selective etching, for example, after eachsuccessive deposition.

[0030] As illustrated in FIG. 6, subsequent to the formation of theconductive material 20 and of the silicon oxide layer 22, the remainingportions 16 a of the photoresist 16, as well as portions of the oxidelayer 14 located below the remaining portions 16 a of the photoresist16, are removed by chemicals so that structures 2 a, 4 a and 6 a remainover the silicon substrate 12. Removal of the remaining portions 16a ofthe photoresist 16 and of the oxide layer 14 located below the remainingportions 16 a may be accomplished by using a KOH solution, hot acetoneor methylethylketone, or by flooding the silicon substrate 12 with UVirradiation to degrade the remaining portions 16 a as well as theportions of the oxide layer 14 located below the remaining portions 16a. As illustrated in FIG. 6, each of the structures 2 a, 4 a and 6 aincludes portions of the oxide layer 14, the barrier layer 18, theconductive material 20 and the silicon oxide layer 22.

[0031] If copper (Cu) is employed as the conductive material 20, a thinpassivation layer, in the range of about 50 Angstroms to about 100Angstroms, may be formed to passivate any exposed copper surfaces, thatis any exposed sidewalls of each of the structures 2 a, 4 a, 6 a of FIG.6. For this, the silicon substrate 12 may be exposed to a dilute silaneat a temperature of about 300° C. to form a thin surface silicide layer24 (FIG. 7) on each of the exposed sidewalls of the conductive material20 of each of the structures 2 a, 4 a, 6 a. This way, the thin surfacesilicide layers 24 complete the fabrication of signal conductor line 2and that of ground conductor planes 4, 6, all illustrated in FIG. 7.

[0032] Alternatively, a thin gold (Au) layer 21 (FIG. 8) of about 10,000Angstroms to about 20,000 Angstroms may be formed on top of the coppermaterial 20 and on each side of the structures 2 a, 4 a and 6 a of FIG.6. The thin gold layer 21 of FIG. 8 may be formed toward the end of thecopper deposition by electroplating, for example.

[0033] Referring now to FIG. 9, deep trenches 26, 28 are next formed inthe silicon substrate 12 by etching, for example, to complete thefabrication of the coplanar waveguide 100. In an exemplary embodiment,anisotropic etching using the silicon oxide layer 22 as a mask isemployed to etch the silicon substrate to a depth of about 100,000Angstroms to about 200,000 Angstroms and to form the deep trenches 26and 28, respectively. The anisotropic etchant may be, for example,potassium hydroxide, tetramethyl ammonium hydrooxide, or ethylenediamine pyrocatecol, among others. Preferably, trenches 26, 28 of FIG. 9are formed by reactive ion etching using a deep trench etcher at an etchrate of about 2.2 μm/min.

[0034] Alternatively, an isotropic etching such as wet etching may beemployed to form trenches 27, 29, as illustrated in FIG. 10, and tocomplete the formation of coplanar waveguide 200. As shown in FIG. 10,each of the trenches 27, 29 has a substantially circular shape, with aradius R of about 50,000 Angstroms to about 100,000 Angstroms.

[0035] The width W (FIG. 9) of the trenches 26, 28 is of about 150,000Angstroms to about 200,000 Angstroms. The width S (FIG. 9) of the signalconductor line 2 is of about 250,000 Angstroms to about 350,000Angstroms, and the thickness T (FIG. 9) from the top surface of thesilicon oxide mask layer 22 to the top surface of the silicon substrate12 is of about 100,000 Angstroms to about 200,000 Angstroms.

[0036] The present invention provides coplanar waveguides 100, 200(FIGS. 9-10) having deep trenches between the signal line and the groundplanes. The coplanar waveguides of the present invention are formed on asilicon substrate of any crystalline orientation and, thus, theirformation is not limited to a silicon substrate of <100> orientation, asin the prior art. In addition, by using an oxide layer below theconductive material, formed preferably of copper, the electric field andthe flux lines in the silicon substrate are minimized and, thus, thesubstrate losses are substantially reduced. Furthermore, the lift-offmetallization process of the present invention for the formation of thesignal conductor and ground planes reduces the number of processingsteps of the prior art and eliminates the need for difficult prior arttechniques, such as deposition of a polyimide and a subsequentplanarization by a two-step chemical mechanical polishing.

[0037]FIG. 11 illustrates a processor system 102, including centralprocessing unit (CPU) 112, RAM and ROM memory devices 108, 110,input/output (I/O) devices 104, 106, floppy disk drive 114 and CD ROMdrive 116. All of the above components communicate with each other overone or more bus systems 118. One or more of the central processing unit(CPU) 112, RAM and ROM memory devices 108, 110 are fabricated on siliconsubstrate 12 with coplanar waveguides, such as the coplanar waveguides100, 200 (FIGS. 9-10) formed in accordance with methods of the presentinvention.

[0038] Although the invention has been described above in connectionwith exemplary embodiments, it is apparent that many modifications andsubstitutions can be made without departing from the spirit or scope ofthe invention. Accordingly, the invention is not to be considered aslimited by the foregoing description, but is only limited by the scopeof the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a coplanar waveguidecomprising the acts of: forming a signal conductor line over asubstrate; forming at least one longitudinal ground conductor plane oversaid substrate and on a side of said signal conductor line, said groundconductor plane being spaced from said signal conductor line; andforming a trench in said substrate in an area between said at least oneground conductor plane and said signal conductor line.
 2. The method ofclaim 1, wherein the acts of forming said signal conductor line and saidground conductor plane further comprise depositing an insulating layeron said substrate and depositing a conductive material on top of saidinsulating layer.
 3. The method of claim 2, wherein said insulatinglayer is an oxide layer.
 4. The method of claim 3 further comprisingdepositing a barrier layer on said oxide layer before depositing saidconductive material.
 5. The method of claim 4, wherein said conductivematerial is a metal layer, said method further comprising forming asilicide layer on sidewalls of said metal layer.
 6. The method of claim3, wherein said oxide layer is deposited to a thickness of about 200Angstroms to about 300 Angstroms.
 7. The method of claim 4, wherein saidbarrier layer is deposited to a thickness of about 50 Angstroms to about100 Angstroms.
 8. The method of claim 4, wherein said barrier layercomprises TiN.
 9. The method of claim 2, wherein said conductivematerial is deposited to a thickness of about 100,000 Angstroms to about200,000 Angstroms.
 10. The method of claim 2, wherein said conductivematerial comprises copper.
 11. The method of claim 2 wherein saidconductive material is deposited by thermal evaporation.
 12. The methodof claim 5, wherein said metal layer is exposed to silane to form saidsilicide layer.
 13. The method of claim 12, wherein said metal layer isexposed to silane at 300° C. to form said silicide layer.
 14. The methodof claim 1, wherein said trench is etched to a depth of about 100,000Angstroms to about 200,000 Angstroms.
 15. The method of claim 1, whereinsaid trench is etched at a rate of about 2.2 μm/min.
 16. The method ofclaim 1, wherein said ground conductor plane is spaced from said signalconductor line by about 150,000 Angstroms to about 200,000 Angstroms.17. The method of claim 1, wherein said signal conductor line has awidth of about 250,000 Angstroms to about 350,000 Angstroms.
 18. Themethod of claim 1, wherein said ground conductor planes and signalconductor line has a thickness of about 100,000 Angstroms to about200,000 Angstroms.
 19. A method of forming a coplanar waveguidecomprising the acts of: forming a signal conductor line over a siliconsubstrate; forming at least one longitudinal ground conductor plane oversaid substrate and on a side of said signal conductor line, said groundconductor plane being spaced from said signal conductor line; andforming at least one trench in said silicon substrate in an area betweensaid at least one ground conductor plane and said signal conductor line,said at least one trench having a depth of about 100,000 Angstroms toabout 200,000 Angstroms and a width of about 100,000 Angstroms to about150,000 Angstroms.
 20. The method of claim 19, wherein the acts offorming said signal conductor line and said ground conductor planefurther comprise depositing an oxide layer on said silicon substrate anddepositing a copper layer on top of said oxide layer.
 21. The method ofclaim 20 further comprising depositing a barrier layer on said oxidelayer before depositing said copper layer.
 22. The method of claim 20further comprising forming a silicide layer on sidewalls of said copperlayer.
 23. The method of claim 20, wherein said oxide layer is depositedto a thickness of about 200 Angstroms to about 300 Angstroms.
 24. Themethod of claim 21, wherein said barrier layer is deposited to athickness of about 50 Angstroms to about 100 Angstroms.
 25. The methodof claim 21, wherein said barrier layer comprises TiN.
 26. The method ofclaim 20, wherein said copper layer is deposited to a thickness of about100,000 Angstroms to about 200,000 Angstroms.
 27. The method of claim22, wherein said copper layer is exposed to silane to form said silicidelayer.
 28. The method of claim 27, wherein said copper layer is exposedto silane at 300° C. to form said silicide layer.
 29. The method ofclaim 19, wherein said ground conductor plane is spaced from said signalconductor line by about 150,000 Angstroms to about 200,000 Angstroms.30. The method of claim 19, wherein said signal conductor line has awidth of about 250,000 Angstroms to about 350,000 Angstroms.
 31. Themethod of claim 19, wherein said ground conductor planes and signalconductor line has a thickness of about 100,000 Angstroms to about200,000 Angstroms.
 32. A method of forming a coplanar waveguidecomprising the acts of: forming a signal conductor line over a siliconsubstrate; forming at least one longitudinal ground conductor plane oversaid substrate and on a side of said signal conductor line, said groundconductor plane being spaced from said signal conductor line; andforming at least one trench in said silicon substrate in an area betweensaid at least one ground conductor plane and said signal conductor line,said at least one trench having a radius of about 50,000 Angstroms toabout 100,000 Angstroms.
 33. The method of claim 32, wherein the acts offorming said signal conductor line and said ground conductor planefurther comprise depositing an oxide layer on said silicon substrate anddepositing a copper layer on top of said oxide layer.
 34. The method ofclaim 33 further comprising depositing a barrier layer on said oxidelayer before depositing said copper layer.
 35. The method of claim 34further comprising forming a silicide layer on sidewalls of said copperlayer.
 36. The method of claim 33, wherein said oxide layer is depositedto a thickness of about 200 Angstroms to about 300 Angstroms.
 37. Themethod of claim 34, wherein said barrier layer is deposited to athickness of about 50 Angstroms to about 100 Angstroms.
 38. The methodof claim 34, wherein said barrier layer comprises TiN.
 39. The method ofclaim 33, wherein said copper layer is deposited to a thickness of about100,000 Angstroms to about 200,000 Angstroms.
 40. The method of claim35, wherein said copper layer is exposed to silane to form said silicidelayer.
 41. The method of claim 41, wherein said copper layer is exposedto silane at 300° C. to form said silicide layer.
 42. The method ofclaim 32, wherein said ground conductor plane is spaced from said signalconductor line by about 150,000 Angstroms to about 200,000 Angstroms.43. The method of claim 32, wherein said signal conductor line has awidth of about 250,000 Angstroms to about 350,000 Angstroms.
 44. Themethod of claim 32, wherein said ground conductor planes and signalconductor line has a thickness of about 100,000 Angstroms to about200,000 Angstroms.
 45. A coplanar waveguide comprising: a substrate; asignal conductor line formed over said substrate; at least twolongitudinal ground conductor planes formed over said substrate on bothsides of said signal conductor line and spaced apart from said signalconductor line to form respective gaps; and at least two trenches formedin said substrate at said respective gaps.
 46. The coplanar waveguide ofclaim 45, wherein said signal conductor line and said ground conductorplanes further comprise an insulating layer on said substrate.
 47. Thecoplanar waveguide of claim 46, wherein said insulating layer is anoxide layer.
 48. The coplanar waveguide of claim 47, wherein said signalconductor line and said ground conductor planes further comprise abarrier layer on said oxide layer.
 49. The coplanar waveguide of claim48, wherein said signal conductor line and said ground conductor planesfurther comprise a conductive material on said barrier layer.
 50. Thecoplanar waveguide of claim 49, wherein said signal conductor line andground conductor planes further comprise silicon oxide on saidconductive material.
 51. The coplanar waveguide of claim 50, whereinsaid signal conductor line and said ground conductor planes comprise asilicide layer on exposed areas of said conductive material.
 52. Thecoplanar waveguide of claim 47, wherein said oxide layer has a thicknessof about 200 Angstroms to about 300 Angstroms.
 53. The coplanarwaveguide of claim 48, wherein said barrier layer has a thickness ofabout 50 Angstroms to about 100 Angstroms.
 54. The coplanar waveguide ofclaim 48, wherein said barrier layer comprises TiN.
 55. The coplanarwaveguide of claim 49, wherein said conductive material has a thicknessof about 100,000 Angstroms to about 200,000 Angstroms.
 56. The coplanarwaveguide of claim 49, wherein said conductive material comprisescopper.
 57. The coplanar waveguide of claim 45, wherein each of said atleast two trenches has a depth of about 100,000 Angstroms to about200,000 Angstroms.
 58. The coplanar waveguide of claim 45, wherein eachof said respective gaps is about 150,000 Angstroms to about 200,000Angstroms.
 59. The coplanar waveguide of claim 45, wherein said signalconductor line has a width of about 250,000 Angstroms to about 350,000Angstroms.
 60. The coplanar waveguide of claim 45, wherein said groundconductor planes and said signal conductor line have a thickness ofabout 100,000 Angstroms to about 200,000 Angstroms.
 61. A processorsystem comprising: a processor; and an integrated circuit coupled tosaid processor, at least one of said integrated circuit and processorcomprising a substrate, a signal conductor line formed over saidsubstrate, at least two longitudinal ground conductor planes formed oversaid substrate and on both sides of said signal conductor line andspaced apart from said signal conductor line to form respective gaps,and at least two trenches formed in said substrate at said respectivegaps.
 62. The system of claim 61, wherein said signal conductor line andsaid ground conductor planes comprise an insulating layer on saidsubstrate and a conductor layer on top of said insulating layer.
 63. Thesystem of claim 62, wherein said insulating layer is an oxide layer. 64.The system of claim 63, wherein said signal conductor line and saidground conductor planes comprise a barrier layer on said oxide layer.65. The system of claim 64, wherein said signal conductor line and saidground conductor planes comprise silicon oxide on said conductor layer.66. The system of claim 65, wherein said signal conductor line and saidground conductor planes comprise a silicide layer on said silicon oxidelayer.
 67. The system of claim 65, wherein said oxide layer has athickness of about 200 Angstroms to about 300 Angstroms.
 68. The systemof claim 64, wherein said barrier layer has a thickness of about 50Angstroms to about 100 Angstroms.
 69. The system of claim 64, whereinsaid barrier layer comprises TiN.
 70. The system of claim 62, whereinsaid conductor layer has a thickness of about 100,000 Angstroms to about200,000 Angstroms.
 71. The system of claim 62, wherein said conductorlayer comprises copper.
 72. The system of claim 61, wherein each of saidat least two trenches has a thickness of about 100,000 Angstroms toabout 200,000 Angstroms.
 73. The system of claim 61, wherein each ofsaid respective gaps is of about 150,000 Angstroms to about 200,000Angstroms.
 74. The system of claim 61, wherein said signal conductorline has a width of about 250,000 Angstroms to about 350,000 Angstroms.75. The system of claim 61, wherein said ground conductor planes andsignal conductor line has a thickness of about 100,000 Angstroms toabout 200,000 Angstroms.
 76. A coplanar waveguide comprising: a siliconsubstrate; a signal conductor line formed over said silicon substrate;at least two longitudinal ground conductor planes formed over saidsilicon substrate on both sides of said signal conductor line and spacedapart from said signal conductor line to form respective gaps; and atleast two trenches formed in said silicon substrate at said respectivegaps, each of said trenches having a depth of about 100,000 Angstroms toabout 200,000 Angstroms and a width of about 100,000 Angstroms to about150,000 Angstroms.
 77. The coplanar waveguide of claim 76, wherein saidsignal conductor line and said ground conductor planes further comprisean oxide layer on said silicon substrate.
 78. The coplanar waveguide ofclaim 77, wherein said signal conductor line and said ground conductorplanes further comprise a barrier layer on said oxide layer.
 79. Thecoplanar waveguide of claim 78, wherein said signal conductor line andsaid ground conductor planes further comprise a copper layer on saidbarrier layer.
 80. The coplanar waveguide of claim 79, wherein saidsignal conductor line and ground conductor planes further comprisesilicon oxide on said copper layer.
 81. The coplanar waveguide of claim80, wherein said signal conductor line and said ground conductor planescomprise a silicide layer on exposed areas of said copper layer.
 82. Thecoplanar waveguide of claim 78, wherein said barrier layer comprisesTiN.
 83. The coplanar waveguide of claim 79, wherein said copper layerhas a thickness of about 100,000 Angstroms to about 200,000 Angstroms.84. A coplanar waveguide comprising: a silicon substrate; a signalconductor line formed over said silicon substrate; at least twolongitudinal ground conductor planes formed over said silicon substrateon both sides of said signal conductor line and spaced apart from saidsignal conductor line to form respective gaps; and at least two trenchesformed in said silicon substrate at said respective gaps, each of saidtrenches having a radius of about 50,000 Angstroms to about 100,000Angstroms.
 85. The coplanar waveguide of claim 84, wherein said signalconductor line and said ground conductor planes further comprise anoxide layer on said silicon substrate.
 86. The coplanar waveguide ofclaim 85, wherein said signal conductor line and said ground conductorplanes further comprise a barrier layer on said oxide layer.
 87. Thecoplanar waveguide of claim 86, wherein said signal conductor line andsaid ground conductor planes further comprise a copper layer on saidbarrier layer.
 88. The coplanar waveguide of claim 87, wherein saidsignal conductor line and ground conductor planes further comprisesilicon oxide on said copper layer.
 89. The coplanar waveguide of claim87, wherein said signal conductor line and said ground conductor planescomprise a silicide layer on exposed areas of said copper layer.
 90. Thecoplanar waveguide of claim 86, wherein said barrier layer comprisesTiN.
 91. The coplanar waveguide of claim 87, wherein said copper layerhas a thickness of about 100,000 Angstroms to about 200,000 Angstroms.